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[ The PC Guide | Systems and Components Reference Guide | The Processor | Processor Families | Sixth Generation Processors ]

Cyrix 6x86MX ("M2")

Cyrix was third to market with a socket-7-compatible MMX processor. The successor to the 6x86 and 6x86L is the 6x86MX, introduced in June 1997 and intended to compete with AMD's K6 and Intel's Pentium with MMX and Pentium II processors. The 6x86MX is an evolutionary step from the 6x86 and is very similar to it in internal function, very much the way the Pentium II is an evolutionary step from the Pentium Pro.

Like the 6x86, the 6x86MX is a native execution, superscalar processor, that is very much like a souped-up Pentium internally. It does not use the RISC core that is now the choice of both Intel and AMD for their high-end CPUs; Cyrix may very well have a good point in their argument that the RISC core is not better, because the 6x86MX has a high ratio of performance to clock speed. The big question, as it was with the 6x86 and AMD's K5 before, is how high can they get the raw clock speed to go? Cyrix fans are fond of pointing out that the Cyrix chips get more performance per unit of clock speed, but of course, the internal design and maximum clock speed are dependent.

The 6x86MX supports the MMX instruction set extension, the same way that its competitors above do, and also features several other improvements over the original 6x86 chip. Much the way the Pentium II's biggest advantage over the Pentium Pro was higher clock speed, the biggest advantage that the 6x86MX has over the 6x86 is higher clock speed as well. Architecturally, most of the improvements in the 6x86MX are tweaks that add together to make a significant difference. The major changes are:

  • Quadrupled Internal Cache: The level 1 cache has been increased from 16 KB to 64 KB on the 6x86MX.
  • Additional Internal Instruction Cache: The 6x86MX includes a small additional level 1 cache (level 0.5 cache??) that is 256 bytes in size and helps improve efficiency in how the regular level 1 cache is operated.
  • Improved Branch Prediction: The branch prediction storage areas are increased in size and the performance improved.
  • 32-Bit Code Optimization: The internal workings of the chip have been optimized for 32-bit operation.

Like its predecessor, the 6x86MX incorporates sufficiently advanced architectural features that it is able to roughly outperform Intel chips of the same clock speed. This means that the "PR" system we grew to know and hate from the 6x86 and AMD's K5 is back (AMD's K6 doesn't really use the "PR" system any more). Cyrix has this time made things even more confusing, if that's possible, because their PR166 and PR200 chips are compared to Intel's Pentium with MMX 166 and 200, but the 6x86MX-PR233 is compared to the Pentium II 233. (I haven't seen any benchmarks yet but I will be surprised if the PR233 is actually close to the Pentium II 233 in real life.)

As with the 6x86 before it, you must be careful to watch out for the way these chips are jumpered, due to the PR business. The true clock speeds of the three chips are 150, 166 and 187 (2.5x75) MHz, respectively, and they should be jumpered this way and not based on what the "PR" rating is. The caveats about the 75 MHz bus speed that I listed in the section on the 6x86 apply to the 6x86MX-PR233 as well.

One of the big criticisms that the original 6x86 got involved the both real and perceived problems with compatibility associated with that chip. These had in large part to due with Cyrix's independent design of the chip. Unfortunately, this has not changed much with the 6x86MX based on information I have researched, although the chip is still very new. The "CPUID" problem is still around. See the section on the 6x86 for more on the compatibility issues.

Physically, at least, the situation is better, as the 6x86MX does not appear to suffer from the voltage and heat problems that plagued the 6x86. The smaller circuit size of the 6x86MX (and of course, the low-powered "L" version of the 6x86) eliminated many of the problems that were experienced by 6x86 users, especially on unapproved motherboards. The 6x86MX is a split rail voltage and uses 3.3 volts for I/O and 2.9 volts for core.

The 6x86MX appears to be a good processor that is going to give Intel and AMD a run for their money. Much as happened with the 6x86, the 6x86MX is positioning itself near the discount end of the market, and is undercutting not just Intel but also AMD significantly in price. In terms of value, the 6x86MX is going to be hard to beat, but it will take time to determine how well this chip is going to work out in the real world.

One thing that clouds the future of the 6x86MX somewhat is the July 1997 acquisition of Cyrix by giant National Semiconductor. The chief executive of National wasted no time in making clear the point that they have no intention of fighting it out head-to-head with AMD and Intel. Apparently, National wants to design a super-integrated "PC on a chip" and target the low-end market heavily. One cannot draw any definitive conclusions about the future of the 6x86MX from this, but it does make one wonder about what will happen with this chip, especially if you are looking for an alternative to the high-end Intel and AMD offerings.

See this web site dedicated to the Cyrix 6x86 family for more information on this processor.

Look here for an explanation of the categories in the processor summary table below, including links to more detailed explanations.

General Information



Family Name


Code name


Processor Generation


Motherboard Generation







June 1997

Variants and Licensed Equivalents

IBM 6x86MX (same chip, marked differently and using different test process)

Speed Specifications

Memory Bus Speed (MHz)




Processor Clock Multiplier


Processor Speed (MHz)




"P" Rating





iCOMP Rating


iCOMP 2.0 Rating


Norton SI


Norton SI32





Physical Characteristics

Process Technology


Circuit Size (microns)


Die Size (mm^2)


Transistors (millions)


Voltage, Power and Cooling

External or I/O Voltage (V)


Internal or Core Voltage (V)


Power Management


Cooling Requirements

Active heat sink


Packaging Style

296-Pin SPGA

Motherboard Interface

Socket 7

External Architecture

Data Bus Width (bits)


Maximum Data Bus Bandwidth (Mbytes/sec)




Address Bus Width (bits)


Maximum Addressable Memory

4 GB

Level 2 Cache Type


Level 2 Cache Size

Usually 256 KB - 512 KB

Level 2 Cache Bus Speed

Same as Memory Bus



Internal Architecture

Instruction Set


MMX Support


Processor Modes

Real, Protected, Virtual Real

x86 Execution Method


Internal Components

Register Size (bits)


Pipeline Depth (stages)


Level 1 Cache Size

64 KB Unified + 0.25 KB Instruction

Level 1 Cache Mapping

4-Way Set Associative

Level 1 Cache Write Policy

Write-Through, Write-Back

Integer Units


Floating Point Unit / Math Coprocessor


Instruction Decoders


Branch Prediction Buffer Size / Accuracy

512 entries / !?

Write Buffers


Performance Enhancing Features

Out of Order Execution, Speculative Execution, Register Renaming, Scratchpad RAM

Next: System Memory (Reference Guide)

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