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In a typical level 2 cache each cache line contains 32 bytes, and transfers to and from the cache occur 32 bytes (256 bits) at a time. The normal transfer paths (for a fifth- or sixth-generation machine) are only 64 bits wide, which means four transfers are done in sequence. Because the transfers are from consecutive memory locations there is no need to specify a different address after the first one; this makes the second, third and fourth accesses extremely fast.
This high-performance access is called "bursting" or using the cache in "burst mode". All modern level 2 caches use this type of access. The timing, in clock cycles, to perform this quadruple read is normally stated as "x-y-y-y". For example, with 3-1-1-1" timing the first read takes 3 clock cycles and the next three take 1 each, for a total of 6. Obviously, the lower these numbers, the better.
Note: This is almost
identical to the way burst transfers are done to and
from memory in modern systems, except faster.
Next: Asynchronous Cache